PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 37. DMA Write Cycle Timing (PD6722 only)
Symbol
Parameter
MIN
MAX
Units
t
t
DRQ (IRQ10) and DACK* (IRQ9) active to DMA cycle begin
40
ns
1
2
-CE[2:1], -REG, -IOWR, -WE, and Write Data setup to -IORD
active1
(S × Tcp) – 10
ns
t
t
t
t
t
t
t
Command: -IORD pulse width2
Recovery: -IORD inactive to end of cycle3
-WAIT active from -IORD active
-WAIT inactive to -IORD inactive
System TC (-VPP_VALID high) to -IORD
-IORD to begin of card TC (-OE)4
End of card TC (-OE) to -IORD inactive4
Data valid from -WAIT inactive
(C × Tcp) – 10
(R × Tcp) – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
6
7
8
9
(C – 2)Tcp – 10
2 Tcp
−40
25
25
50
50
t
Tcp + 10
(2 Tcp) +10
0
10
t
Data setup before -OE inactive
Data hold after -OE inactive
11
t
12
1. The Setup time is determined by the value programmed into the Setup Timing register, index 3Ah/3Dh. Using the Timer Set
0 default value of 01h, the setup time would be 70 ns. S = (N
page 109.
× N + 1), see “PC Card Bus Timing Calculations” on
pres
val
2. The Command time is determined by the value programmed into the Command Timing register, index 3Bh/3Eh. Using the
Timer Set 0 default value of 06h, the Command time would be 270 ns. C = (N × N + 1), see page 109.
pres
val
3. The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the
Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns. R = (N
4. Based on an internal clock period of 40 ns (25 MHz).
× N + 1), see page 109.
pres
val
118
Datasheet
INTEL [ INTEL ]
