ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
16.4.1
Reset Timing
Table 27. Reset Timing
Symbol
Parameter
MIN
MAX
Units
t
t
t
PWRGOOD generated reset pulse width
Clock active before end of reset1
500
500
500
ns
ns
ns
1
2
3
End of PWRGOOD generated reset to first Command
1. Clock input must be active for a minimum of 500 ns before PWRGOOD goes active to allow sufficient internal clocks to
initialize internal circuitry.
Figure 19. Reset Timing
t1
PWRGOOD
t2
CLK
MEMR*, MEMW*
IOR*, IOW*
t3
16.4.2
System Interrupt Timing
Table 28. Pulse Mode Interrupt Timing
Symbol
Parameter
MIN
MAX
t
IRQ[XX] low or high
2 CLK – 10 ns
2 CLK + 10 ns
1
Datasheet
107
INTEL [ INTEL ]
