PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Figure 20. Pulse Mode Interrupt Timing
High-Z
High-Z
IRQ[XX]
t
t
1
1
High-Z = high impedance
NOTE: Each time indicated is 2 clock periods of the CLK input to the PD67XX, independent of setting of the
Bypass Frequency Synthesizer bit.
16.4.3
General-Purpose Strobe Timing (PD6722 only)
Table 29. General-Purpose Strobe Timing
Symbol
Parameter
MIN
MAX
Units
t
t
GPSTB delay after IOR* or IOW* active
GPSTB delay after IOR* or IOW* inactive
40
40
ns
ns
1
2
Figure 21. General-Purpose Strobe Timing
t2
t1
IOR*, IOW*
GPSTB
16.4.4
Input Clock Specification
Table 30. Input Clock Specification (Sheet 1 of 2)
Symbol
Parameter
MIN
MAX
Units
Conditions
t
t
t
t
CLK pin input rise time
CLK pin input fall time
CLK input low period
CLK input high period
1
1
7
7
ns
ns
ns
ns
1
2
3
4
0.4 T
0.6 T
CLKP
CLKP
CLKP
CLKP
0.4 T
0.6 T
Center voltage at which period
specified
V
0.5 V
0.5 V
DD
V
center
DD
108
Datasheet
INTEL [ INTEL ]
