ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 30. Input Clock Specification (Sheet 2 of 2)
Symbol
Parameter
MIN
MAX
Units
Conditions
Normal synthesizer
Input clock period,
internal clock
operation. Misc Control 2
register, bit 0 = ‘0’. CLK
pin at 14.318 MHz.
T
69.84 – 0.1%
69.84 + 0.1%
ns
CLKP
Synthesizer bypassed.
Misc Control 2 register,
bit 0 = ‘1’.
Input clock period,
external clock
T
V
40 – 0.1%
40 + 0.1%
ns
CLKP
CLK pin at 25 MHz.
CLK input high voltage
CLK input low voltage
CLK input high voltage
CLK input low voltage
2.0
V
V
V
V
CORE_VDD = 3.0 V
CORE_VDD = 3.6 V
CORE_VDD = 4.5 V
CORE_VDD = 5.5 V
IHmin
ILmax
V
0.8
V
V
0.7 V
DD
IHCmin
ILCmax
0.2 V
DD
Figure 22. Input Clock Specification
t
1
t
2
V
, V
IHmin IHCmin
V
center
V
, V
ILmax ILCmax
CLK
t
t
4
3
T
CLKP
16.4.5
PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by
first calculating factors derived from the applicable timer set’s timing registers and then by
applying the factor to an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as
follows:
S = (Npres × Nval) + 1
C = (Npres × Nval) + 1
R = (Npres × Nval) + 1
Datasheet
109
INTEL [ INTEL ]
