3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
The Read Configuration mode outputs three types of information: the manufacturer/device
identifier, the block locking status, and the protection register. The device is switched to this mode
by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses
shown in Table 4 retrieve the specified information. To return to read array mode, write the Read
Array command (FFh).
Table 4. Read Configuration Table
Item
Address
Data
Notes
Manufacturer Code (x16)
Device ID (See Appendix D)
Block Lock Configuration
0x00000
0x00001
0xXX002
0x0089
ID
LOCK
1, 2
•
•
•
Block Is Unlocked
Block Is Locked
DQ = 0
0
DQ = 1
0
Block Is Locked-Down
DQ = 1
1
Protection Register Lock
Protection Register (x16)
NOTES:
0x80
PR-LK
PR
3
0x81-0x88
1. See Section 3.7 for valid lock status outputs.
2. “XX” specifies the block address of lock configuration being read.
3. See Section 3.8 for protection register information.
Other locations within the configuration address space are reserved by Intel for future use.
3.3
Read Status Register (70h)
The status register indicates the status of device operations, and the success/failure of that
operation. The Read Status Register (70h) command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the array, issue a
Read Array (FFh) command.
The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a
Read Status Register command.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever
occurs last. This prevents possible bus errors which might occur if status register contents change
while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status
register will not indicate completion of a program or erase operation.
When the WSM is active, SR7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether the WSM was successful in performing the desired operation (see
Table 6, “Flash Memory Status Register Definition” on page 18).
3.3.1
Clear Status Register (50h)
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these
bits can only be cleared through the use of the Clear Status Register (50h) command. By allowing
the system software to control the resetting of these bits, several operations may be performed
14
Datasheet
INTEL [ INTEL ]
