3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
2.1.4
Flash Reset
The device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or
tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal
operation is restored. The device defaults to read array mode, the status register is set to 80h, and
the read configuration register defaults to asynchronous reads.
If RP# is taken low during a block erase or program operation, the operation will be aborted and the
memory contents at the aborted location are no longer valid.
2.1.5
Write
Writes to flash take place when both F-CE# and F-WE# are asserted and F-OE# is deasserted.
Writes to SRAM take place when both S-CS1# and S-WE# are asserted and S-OE# and S-CS2 are
deasserted. Commands are written to the flash memory’s Command User Interface (CUI) using
standard microprocessor write timings to control flash operations. The CUI does not occupy an
addressable memory location within the flash component. The address and data buses are latched
on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 and
Figure 7 for read and write waveforms.)
3.0
Flash Memory Modes of Operation
The flash memory has four read modes: read array, read configuration, read status, and CFI query.
The write modes are program and erase. Three additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are available only during suspended operations.
These modes are reached using the commands summarized in Table 5, “Flash Memory Command
Definitions” on page 17.
3.1
Read Array (FFh)
When F-RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will
respond to the read control inputs without any additional CUI commands.
In addition, the address of the desired location must be applied to the address balls. If the device is
not in read array mode, as would be the case after a program or erase operation, the Read Array
command (FFh) must be written to the CUI before array reads can take place.
3.2
Read Identifier (90h)
The read configuration mode outputs the manufacturer/device identifier. The device is switched to
this mode by writing the read configuration command (90h). Once in this mode, read cycles from
addresses shown in Table 4, “Read Configuration Table” on page 14 retrieve the specified
information. To return to read array mode, write the Read Array command (FFh).
Datasheet
13
INTEL [ INTEL ]
