3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 5. Flash Memory Command Definitions
First Bus Cycle
Address
Second Bus Cycle
Command
Note
Operation
Data
Operation
Address
Data
Read Array
1
1, 2
1, 2
1
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FFh
90h
Read Identifier
Read
Read
Read
IA
QA
X
ID
QD
CFI Query
98h
Read Status Register
Clear Status Register
Word Program
70h
SRD
1
50h
1, 3
1
40h/10h
20h
Write
Write
PA
BA
PD
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
Lock Block
D0h
1
B0h
D0h
60h
1
1
Write
Write
Write
Write
Write
BA
BA
BA
PA
PA
01h
D0h
2Fh
Unlock Block
1, 4
1
60h
Lock-Down Block
Protection Register Program
Lock Protection Register
60h
1
C0h
C0h
PD
1
FFFD
X = Don’t Care
PA = Program Address BA = Block Address
IA = Identifier Address QA = Query Address
ID = Identifier Data QD = Query Data
SRD = Status Register Data PD = Program Data
NOTES:
1. When writing commands, the upper data bus [DQ –DQ ] should be either V or V , to minimize current draw.
8
15
IL
IH
2. Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query
information, respectively.
3. Either 40h or 10h command is valid, but the Intel standard is 40h.
4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Datasheet
17
INTEL [ INTEL ]
