3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 6. Flash Memory Status Register Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
Check Write State Machine bit first to determine Word Program or
Block Erase completion, before checking Program or Erase Status
bits.
0 = Busy
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an
Erase Resume command is issued.
0 = Erase In Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
When this bit is set to “1,” WSM has applied the max. number of
erase pulses and is still unable to verify successful block erasure.
0 = Successful Block Erase
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
0 = Successful Programming
SR.3 = F-V STATUS (VPPS)
The F-V status bit does not provide continuous indication of V
PP PP
PP
1 = F-V Low Detect, Operation Abort
level. The WSM interrogates F-V level only after the Program or
PP
PP
0 = F-V OK
Erase command sequences have been entered, and informs the
PP
system if F-V has not been switched on. The F-V is also
PP
PP
checked before the operation is verified by the WSM. The F-V
PP
status bit is not guaranteed to report accurate feedback between
and V min.
V
PPLK
PP1
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
When Program Suspend is issued, WSM halts execution and sets
both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a
Program Resume command is issued.
0 = Program in Progress/Completed
SR.1 = BLOCK LOCK STATUS
If a program or erase operation is attempted to one of the locked
1 = Prog/Erase attempted on a locked block; Operation blocks, this bit is set by the WSM. The operation specified is
aborted.
aborted and the device is returned to read status mode.
0 = No operation to locked blocks
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when
polling the status register.
NOTE: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
3.7
Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked
with no latency, which enables instant code and data protection.
This locking offers two levels of protection. The first level allows software-only control of block
locking (useful for data blocks that change frequently), while the second level requires hardware
interaction before locking can be changed (useful for code blocks that change infrequently).
The following sections will discuss the operation of the locking system. The term “state [XYZ]”
will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ1 of
the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 8, “Block
Locking State Transitions” on page 21 defines all of these possible locking states.
18
Datasheet
INTEL [ INTEL ]
