3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 3. 3 Volt Intel Advanced+ Boot Block Flash Memory Stacked-CSP Bus Operations
Flash Signals
SRAM Signals
Memory Output
Modes
Notes
D –
0
D
15
Read
H
H
H
H
L
L
L
L
H
X
H
X
H
L
Flash
Flash
Other
Other
Other
SRAM
SRAM
D
2,3,4
2,4
5,6
5,6
5,6
2,4
2,4
OUT
SRAM must be in High Z
Write
D
IN
Standby
Output Disable
Reset
H
L
X
H
X
High Z
High Z
High Z
Any SRAM mode is allowable
X
Read
L
L
H
H
X
L
L
H
X
X
H
H
L
L
L
D
FLASH must be in High Z
OUT
Write
D
IN
H
X
L
X
X
H
X
X
X
Standby
Other
High Z
4,5,6
Any FLASH mode is allowable
Output Disable
Data Retention
H
Other
Other
High Z
High Z
4,5,6
4,5,7
same as a standby
NOTES:
1. Two devices may not drive the memory bus at the same time.
2. The SRAM may be placed into data retention mode by lowering the S-V to the V range, as specified.
CC
DR
2.1.2
Output Disable
With F-OE# and S-OE# deasserted, the Stacked-CSP outputs signals are placed in a high-
impedance state.
2.1.3
Standby
With F-CE# and S-CS1# or S-CS2 deasserted, the Stacked-CSP enters a standby mode, which
substantially reduces device power consumption. In standby, outputs are placed in a high-
impedance state independent of F-OE# and S-OE#. If the flash is deselected during a program or
erase operation, the flash continues to consume active power until the program or erase operation is
complete.
12
Datasheet
INTEL [ INTEL ]
