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RD28F1602C3B110 参数 Datasheet PDF下载

RD28F1602C3B110图片预览
型号: RD28F1602C3B110
PDF下载: 下载PDF文件 查看货源
内容描述: 3 VOLT英特尔?高级+引导?座闪存?记忆? ( C3) ?堆叠芯片? ScalPackage ? Familye [3 VOLT INTEL Advanced+BootBlock FlashMemory(C3)Stacked-ChipScalPackageFamilye]
分类和应用: 闪存存储内存集成电路静态存储器
文件页数/大小: 70 页 / 1167 K
品牌: INTEL [ INTEL ]
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family  
2. To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should  
be connected directly to the land pad for ball G4 (A17).  
1.4  
Signal Definitions  
Table 2. defines the signal definitions shown in the previous ballout.  
Table 2. 3 Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet 1 of 2)  
Symbol  
Type  
Name and Function  
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or  
erase cycle.  
2-Mbit : A[16:0]  
4-Mbit : A[18:0]  
16-Mbit : A[19:0]  
32-Mbit A[20:0]  
A[20:0]  
INPUT  
DATA INPUTS/OUTPUTS: Inputs array data for SRAM write operations and on the second F-CE#  
and F-WE# cycle during a flash program command. Inputs commands to the flash’s Command  
User Interface when F-CE# and F-WE# are asserted. Data is internally latched. Outputs array,  
configuration and status register data. The data balls float to tri-state when the chip is de-selected  
or the outputs are disabled.  
INPUT /  
OUTPUT  
DQ[15:0]  
FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders and  
sense amplifiers. F-CE# is active low. F-CE# high de-selects the flash memory device and reduces  
power consumption to standby levels.  
F-CE#  
S-CS1#  
S-CS2  
INPUT  
INPUT  
INPUT  
SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and  
sense amplifiers. S-CS1# is active low. S-CS1# high de-selects the SRAM memory device and  
reduces power consumption to standby levels.  
SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and  
sense amplifiers. S-CS2 is active high. S-CS2 low de-selects the SRAM memory device and  
reduces power consumption to standby levels.  
FLASH OUTPUT ENABLE: Enables flash’s outputs through the data buffers during a read  
operation. F-OE# is active low.  
F-OE#  
S-OE#  
INPUT  
INPUT  
SRAM OUTPUT ENABLE: Enables SRAM’s outputs through the data buffers during a read  
operation. S-OE# is active low.  
FLASH WRITE ENABLE: Controls writes to flash’s command register and memory array. F-WE#  
is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse.  
F-WE#  
S-WE#  
S-UB#  
INPUT  
INPUT  
INPUT  
SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low.  
SRAM UPPER BYTE ENABLE: Enables the upper byte for SRAM (DQ –DQ ).  
8
15  
S-UB# is active low.  
SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ –DQ ).  
S-LB# is active low.  
0
7
S-LB#  
INPUT  
FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (V , V ) to control reset/deep  
IL  
IH  
power-down mode.  
When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the  
outputs to High-Z, resets the Write State Machine, and minimizes current levels (I ).  
F-RP#  
INPUT  
CCD  
When F-RP# is at logic high, the device is in standard operation. When F-RP# transitions from  
logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.  
Datasheet  
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