E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
2.7
0.0
OUTPUT
INPUT
1.35
TEST POINTS
1.35
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35
V. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V
3.0
OUTPUT
INPUT
1.5
TEST POINTS
1.5
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V and VCC = 5.0 V ± 5%
(High Speed Testing Configuration)
2.4
2.0
0.8
2.0
0.8
INPUT
OUTPUT
TEST POINTS
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and V (0.45 VTTL) for a Logic "0." Input timing begins at V
IH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. OInLput rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for VCC = 5.0 V ± 10%
(Standard Testing Configuration)
Test Configuration Capacitance Loading Value
1.3V
Test Configuration
VCC = 3.3 V ± 0.3 V, 2.7 V−3.6 V
VCC = 5 V ± 5%
CL (pF)
50
1N914
30
RL
= 3.3 K
DEVICE
UNDER
TEST
VCC = 5 V ± 10%
100
OUT
CL
NOTE:
CL includes Jig Capacitance
Figure 16. Transient Equivalent Testing
Load Circuit
33
PRELIMINARY
INTEL [ INTEL ]
