E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
(1,2)
6.6
AC Characteristics—Write Operations
—Commercial Temperature
TA = 0°C to +70°C
5 V ± 5%,
5 V ± 10% VCC
Valid for All
Speeds
3.3 V ± 0.3 V,
2.7 V−3.6 V VCC
Valid for All
Speeds
Versions
Unit
#
Sym
Parameter
Notes Min Max Min Max
W1 tPHWL (tPHEL
)
RP# High Recovery to WE# (CE#) Going
Low
3
1
1
µs
ns
W2 tELWL (tWLEL
)
CE# (WE#) Setup to WE# (CE#) Going
Low
7
0
0
W3 tWP
W4 tDVWH (tDVEH
W5 tAVWH (tAVEH
W6 tWHEH (tEHWH
W7 tWHDX (tEHDX
Write Pulse Width
7
4
4
50
40
40
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
)
)
)
5
5
W8 tWHAX (tEHAX
)
5
5
W9 tWPH
9
25
100
100
0
25
100
100
0
W10 tPHHWH (tPHHEH
W11 tVPWH (tVPEH
W12 tWHGL (tEHGL
) RP# VHH Setup to WE# (CE#) Going High 3,8
)
VPP Setup to WE# (CE#) Going High
Write Recovery before Read
3,8
)
W13 tWHRL (tEHRL
)
WE# (CE#) High to RY/BY# Going Low
8
90
90
W14 tQVPH
RP# VHH Hold from Valid SRD, RY/BY#
High
3,5,8
0
0
0
0
W15 tQVVL
VPP Hold from Valid SRD, RY/BY# High
3,5,8
ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration.
5.
V
PP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH) until determination of block erase, program,
or lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Ordering Information for device speeds (valid operational combinations).
7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to tWP – 10 ns for 5 V VCC and tWP – 20 ns for 2.7 V and 3.3 V VCC writes.
8. Block erase, program, and lock-bit configuration withV
< 3.0 V should not be attempted.
CC
9. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
37
PRELIMINARY
INTEL [ INTEL ]
