BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
6.4 DC Characteristics—Commercial Temperature(Continued)
E
2.7 V V
3.3 V V
CC
5 V V
Test
Conditions
CC
CC
Sym
Parameter
Input Low Voltage
Input High Voltage
Notes Min Max Min Max Min Max Unit
V
7
–0.5 0.8 –0.5 0.8 –0.5 0.8
V
V
IL
V
7
2.0
2.4
V
2.0
V
2.0 V
CC
IH
CC
CC
+ 0.5
0.4
+ 0.5
0.4
+ 0.5
0.45
V
Output Low Voltage
3,7
3,7
V
V
I
= V
Min
CC
OL
CC
= 2 mA (2.7V, 3.3V)
5.8 mA (5V)
OL
V
V
Output High Voltage (TTL)
2.4
2.4
V
V
V
V
I
= V
Min
CC
OH1
OH2
CC
= –2.5 mA
OH
Output High Voltage
(CMOS)
3,7 0.85
0.85
0.85
V
I
= V
Min
CC
CC
= –2.5 mA
V
V
V
CC
CC
CC
OH
V
V
V
V
I
= V
Min
CC
CC
CC
CC
CC
= –100 µA
–0.4
–0.4
–0.4
OH
V
V
V
V
V
Lockout Voltage
Voltage
4,7
8,9
1.5
1.5
1.5
V
V
PPLK PP
V
3.0 3.6
PPH1 PP
V
Voltage
4.5 5.5 4.5 5.5
11.4 12.6 11.4 12.6
PPH2 PP
V
Voltage
V
PPH3 PP
V
V
V
Lockout Voltage
CC
2.0
2.0
2.0
V
V
LKO
HH
RP# Unlock Voltage
11.4 12.6 11.4 12.6
Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominalVCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2.
I
CCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of ICCWS or ICCES and ICCR or ICCW
3. Includes RY/BY#.
.
4. Block erases, programs, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), between VPPH2 (max) and VPPH3 (min), and
above VPPH3 (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH
7. Sampled, not 100% tested.
.
8. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the
master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with VIH < RP# < VHH
.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
32
PRELIMINARY
INTEL [ INTEL ]
