28F640L30, 28F128L30, 28F256L30
5.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and
programming algorithms. However, factory word programming enhances the programming
performance with VPP = VPPH. This can enable faster programming times during OEM
manufacturing processes. Factory word programming is not intended for extended use. See Section
11.2, “Operating Conditions” on page 52 for limitations when VPP = VPPH
.
Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven
by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH
the device draws programming current from the VPP supply. Figure 7, “Example VPP Supply
Connections” on page 35 shows examples of device power supply configurations.
,
5.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For Buffered
Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed
into the flash memory array in buffer-size increments. This can improve system programming
performance significantly over non-buffered programming.
When the Buffered Programming Setup command is issued (see Section 3.2, “Device Commands”
on page 18), Status Register information is updated and reflects the availability of the buffer. SR[7]
indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To
retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is
set, the buffer is ready for loading. (see Figure 32, “Buffered Program Flowchart” on page 76).
On the next write, a word count is written to the device at the buffer address. This tells the device
how many data words will be written to the buffer, up to the maximum size of the buffer.
On the next write, a device start address is given along with the first data to be written to the flash
memory array. Subsequent writes provide additional device addresses and data. All data addresses
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning of a 32-word
boundary (A[4:0] = 0x00). A misaligned starting address doubles the total program time.
After the last data is written to the buffer, the Buffered Programming Confirm command must be
issued to the original block address. The WSM begins to program buffer contents to the flash
memory array. If a command other than the Buffered Programming Confirm command is written to
the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error
occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4]
are set, indicating a programming failure.
Reading from another partition is allowed while data is being programmed into the array from the
write buffer (see Figure 38, “Read While Buffered Programming Flowchart” on page 82).
When Buffered Programming has completed, an additional buffer writes can be initiated by issuing
another Buffered Programming Setup command and repeating the buffered program sequence.
Buffered programming may be performed with VPP = VPPL or VPPH (see Section 11.2, “Operating
Conditions” on page 52 for limitations when operating the device with VPP = VPPH).
When Status Register bits SR[5,4] are set, the device does not accept Buffered Program
commands. If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command sequence error, and
Status Register bits SR[5,4] are set.
Datasheet
31
INTEL [ INTEL ]
