28F640L30, 28F128L30, 28F256L30
If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are
set. If any errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
5.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash
programming for today's beat-rate-sensitive manufacturing environments. The enhanced
programming algorithm used in Buffered EFP eliminates traditional programming elements that
drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 33, “Buffered
EFP Flowchart” on page 77). It uses a write buffer to spread MLC program performance across 32
data words. Verification occurs in the same phase as programming to accurately program the flash
memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each set of 32 data
words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0]
indicates when data from the buffer has been programmed into sequential flash memory array
locations.
Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)
increments internal addressing to automatically select the next 32-word array boundary. This
aspect of Buffered EFP saves host programming equipment the address-bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the device has programmed properly. This eliminates the external post-
program verification and its associated overhead.
5.3.1
Buffered EFP Requirements and Considerations
Buffered EFP requirements:
• Ambient temperature: TA = 25°C, ±5°C
• VCC within specified operating range.
• VPP driven to VPPH
.
• Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.
• The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired.
• WA0 must align with the start of an array buffer boundary1.
Buffered EFP considerations:
• For optimum performance, cycling must be limited below 100 erase cycles per block2.
• Buffered EFP programs one block at a time; all buffer data must fall within a single block3.
• Buffered EFP cannot be suspended.
• Programming to the flash memory array can occur only when the buffer is full4.
32
Datasheet
INTEL [ INTEL ]
