28F640L30, 28F128L30, 28F256L30
3.0
3.1
Device Operations
This section provides an overview of device operations. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus. The on-chip Write State
Machine (WSM) manages all block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash memory
device operations. The CUI does not occupy an addressable memory location; it is the mechanism
through which the flash device is controlled.
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes upper
address inputs to determine the accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through
if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising
ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must
be VIL).
3.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See Section 4.0, “Read Operations” on page 22 for details on the available read modes, and see
Section 9.0, “Special Read States” on page 47 for details regarding the available read states.
The Automatic Power Savings (APS) feature provides low power operation following reads during
active mode. After data is read from the memory array and the address lines are quiescent, APS
automatically places the device into standby. In APS, device current is reduced to ICCAPS (see
Section 11.3, “DC Current Characteristics” on page 53).
3.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted.
During a write operation, address and data are latched on the rising edge of WE# or CE#,
whichever occurs first. Table 5, “Command Bus Cycles” on page 19 shows the bus cycle sequence
for each of the supported device commands, while Table 6, “Command Codes and Definitions” on
page 20 describes each command. See Section 12.0, “AC Characteristics” on page 55 for signal-
timing details.
Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not
be attempted.
3.1.3
Output Disable
When OE# is deasserted, device outputs D[15:0] are disabled and placed in a high-impedance
(High-Z) state, WAIT is also placed in High-Z.
Datasheet
17
INTEL [ INTEL ]
