Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figure 10. Overview of Link Establishment
Power-Up, Reset,
Link Failure
Start
Disable
Auto-Negotiation
Enable
0.12 = 0
0.12 = 1
Auto-Neg/Parallel Detection
Check Value
0.12
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 100TX
Idle Symbols
Listen for 10T
Link Pulses
YES
NO
Done
Link Set
1.9
MII Operation
Figure 11 is a simple block diagram of the MII data interface. Separate channels are provided for
transmitting data from the MAC to the LXT9763 (TXD), and for passing data received from the
line to the MAC (RXD). Each channel has its own clock, data bus, and control signals. Nine signals
are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL and
CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and
TX_ER. The LXT9763 supplies both transmit and receive clock signals as well as separate outputs
for carrier sense and collision.
Data is normally exchanged across the MII in 4-bit-wide nibbles. However, two alternative data
exchange methods are provided. A 5-bit symbol mode is available via bit 16.11 for 100M
operation. Refer to Table 47 on page 68 for additional information on these bit settings.
Datasheet
25
INTEL [ INTEL ]
