LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Figure 11. MII Data Interface
TX_CLKn
TX_ENn
TXD<3:0>n
TX_ERn
Media
Access
Controller
(MAC)
RX_CLKn
RX_DVn
RXD<3:0>n
RX_ERn
CRSn
Orca_6M
COLn
1.9.1
Transmit Clock
The LXT9763 is the master clock source for data transmission. It automatically sets the speed of
TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK will be set to 25
MHz. If the port is operating at 10 Mbps, TX_CLK will be set to 2.5 MHz. The transmit data and
control signals must always be synchronized to TX_CLK by the MAC. The LXT9763 samples
these signals on the rising edge of TX_CLK.
1.9.2
1.9.3
Transmit Enable
The MAC must assert TX_EN synchronously with the first nibble of preamble, and de-assert
TX_EN after the last bit of the packet.
Receive Data Valid
The LXT9763 asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
• For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the
data packet.
• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of
the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
1.9.4
Error Signals
Whenever the LXT9763 receives an errored symbol from the network, it asserts RX_ER and drives
“1110” on the RXD pins. RX_ER is synchronous with RX_CLK.
When the MAC asserts TX_ER, the LXT9763 will drive “H” symbols out on the line. TX_ER
must be synchronous with TX_CLK.
26
Datasheet
INTEL [ INTEL ]
