LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 8. Carrier Sense, Loopback, and Collision Conditions
Test1
Loopback
Operational
Loopback
Speed
Duplex Condition
Carrier Sense
Collision
Full-Duplex
Receive Only
Transmit or Receive
Receive Only
Yes
No
No
No
No
Yes
No
None
100 Mbps
Half-Duplex
Transmit and Receive
None
Full-Duplex
Yes
No
10 Mbps
Half-Duplex, 16.8 = 0
Half-Duplex, 16.8 = 1
Transmit or Receive
Transmit or Receive
Transmit and Receive
Transmit and Receive
None
1. Test Loopback is enabled when 0.14 = 1
1.10
100 Mbps Operation
1.10.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT9763 transmits and receives 5-bit symbols across the
network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not
actively transmitting data, the LXT9763 sends out Idle symbols on the line.
As shown in Figure 13, the MAC starts each transmission with a preamble pattern. As soon as the
LXT9763 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol
to the network. It then encodes and transmits the rest of the packet, including the balance of the
preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the
LXT9763 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to
transmitting Idle symbols.
In 100TX mode, the LXT9763 scrambles the data and transmits it to the network using MLT-3 line
code. The MLT-3 signals received from the network are descrambled and decoded and sent across
the MII to the MAC. Figure 14 shows the internal signal flow between the MII and the network
interface.
In 100FX mode, the LXT9763 transmits and receives NRZI signals across the PECL interface. An
external 100FX transceiver module is required to complete the fiber connection.
Figure 13. 100BASE-X Frame Format
64-Bit Preamble
(8 Octets)
Destination and Source
Address (6 Octets each)
Packet Length
(2 Octets)
Data Field
(Pad to minimum packet size)
Frame Check Field InterFrame Gap / Idle Code
(4 Octets)
(> 12 Octets)
CRC
IFG
SFD
P0 P1 P6
DA DA SA SA L1
L2 D0 D1 Dn
I0
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
Replaced by
Start-of-Frame
Delimiter (SFD)
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
28
Datasheet
INTEL [ INTEL ]
