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LXT9763HC 参数 Datasheet PDF下载

LXT9763HC图片预览
型号: LXT9763HC
PDF下载: 下载PDF文件 查看货源
内容描述: LAN收发器| HEX | QFP | 208PIN |塑料\n [LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC ]
分类和应用: 网络接口电信集成电路电信电路局域网以太网:16GBASE-T
文件页数/大小: 74 页 / 973 K
品牌: INTEL [ INTEL ]
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Fast Ethernet 10/100 Hex Transceiver with Full MII LXT9763  
1.9.5  
1.9.6  
Carrier Sense  
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received  
from the network and in some modes when a packet is transmitted.  
On transmit, CRS is asserted on a 10 Mbps or 100 Mbps half-duplex link. Carrier sense is not  
generated on transmit when the link is operating in full-duplex mode.  
Collision  
The LXT9763 asserts its collision signal, asynchronously to any clock, whenever the line state is  
half-duplex and the transmitter and receiver are active at the same time. Table 8 summarizes the  
conditions for assertion of carrier sense, collision, and data loopback signals.  
1.9.7  
Loopback  
The LXT9763 provides two loopback functions, operational and test (see Table 8).  
1.9.7.1  
Operational Loopback  
Operational loopback is provided for 10 Mbps half-duplex links when bit 16.8 = 0. Data  
transmitted by the MAC (TXData) will be looped back on the receive side of the MII (RXData).  
Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.  
1.9.7.2  
Test Loopback  
A test loopback function is provided for diagnostic testing of the LXT9763. During test loopback,  
twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped  
back by the LXT9763 and returned to the MAC.  
Test loopback is available for 100TX, 100FX, and 10T operation. Test loopback is enabled by  
setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). Loopback  
paths are shown in Figure 12.  
Figure 12. Loopback Paths  
LXT9763  
FX Driver  
TX Driver  
10T  
Loopback  
Digital  
Block  
100X  
Loopback  
Analog  
Block  
MII  
Datasheet  
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