Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figure 14. 100BASE-TX Data Path
Standard Data Flow
+1
Parallel
D0
to
0
0
0
Serial
Scramble
D1
-1
4B/5B
MLT3
D0 D1 D2 D3
S0 S1 S2 S3 S4
De-
Scramble
D2
Transition = 1.
No Transition = 0.
Serial
to
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
D3
Parallel
Symbol (5B) Mode Data Flow
S0
Parallel
+1
to
Serial
S1
0
0
0
Scramble
-1
S2
S0 S1 S2 S3 S4
MLT3
De-
Scramble
Serial
to
Parallel
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
S3
S4
Scrambler Bypass Data Flow
S0
+1
Parallel
to
Serial
S1
0
0
0
-1
4B/5B
MLT3
S2
S3
S4
D0 D1 D2 D3
S0 S1 S2 S3 S4
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Serial
to
Parallel
1.10.2
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT9763 is a Physical Layer 1 (PHY)
device. The LXT9763 implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u specification. The following paragraphs discuss LXT9763 operation
from the reference model point of view.
1.10.2.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function. (For symbol mode operation, the 4B/5B function can be bypassed by setting
16.11 = 1.)
For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line
driver as long as TX_EN is de-asserted.
Datasheet
29
INTEL [ INTEL ]
