Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
1.7
Hardware Configuration Settings
The LXT9763 provides a hardware option to set the initial device configuration. The hardware
option uses the three LED/CFG pins for each port. This provides three control bits per port, as
listed in Table 7. The LED drivers can operate as either open drain or open source circuits as shown
in Figure 9. The LED pins are sensitive to polarity and will automatically pull up or pull down to
configure for either open drain or open source circuits (10 mA max current rating) as required by
the hardware configuration. In applications where all ports are configured the same, several pins
may be tied together with a single resistor.
Note: Fiber operation cannot be selected via hardware. Fiber operation must be enabled via the MDIO
port.
.
Figure 9. Hardware Configuration Settings
VCC
Configuration Bit = 1
LED/CFG Pin
LED/CFG Pin
Configuration Bit = 0
1. LEDs will automatically correct
their polarity upon power-up or
Table 7. Hardware Configuration Settings
Desired Configuration
Pin Settings
Resulting Register Bit Values
Control Register AN Advertisement Register
LED/CFGn_1
AutoNeg
Mode
Speed
Mode
Duplex
Mode
AutoNeg
0.12
Speed
0.13
FD
0.8
100FD
4.8
100TX
4.7
10 FD
4.6
10T
4.5
1
2
3
Half
Full
Half
Full
Half
Full
Half
Full
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10
100
0
1
X X X X 2
Disabled
0
Auto-Negotiation
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0
1
0
1
100
0
0
1
Enabled3
1
1
1
0
10/100
1
1. These pins set the default values for registers 0 and 4 accordingly.
2. X = Don’t Care.
3. Do not select Fiber mode with Auto-Negotiation enabled.
Datasheet
23
INTEL [ INTEL ]
