Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figure 4. Port Address Scheme
BASE ADDR
(ex. ADDR=4)
LXT9763
PHY ADDR (BASE+0)
ex. 4
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
PHY ADDR (BASE+1)
ex. 5
PHY ADDR (BASE+2)
ex. 6
PHY ADDR (BASE+3)
ex. 7
PHY ADDR (BASE+4)
ex. 8
PHY ADDR (BASE+5)
ex. 9
1.3.0.1
MII Interrupts
The LXT9763 provides a single interrupt pin available to all ports. Interrupt logic is shown in
Figure 7. The LXT9763 also provides two dedicated interrupt registers for each port. Register 18
provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting bit
18.1 = 1, enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates
a status change on the LXT9763. However, because it is a shared interrupt, it does not indicate
which port is requesting service. Interrupts may be caused by one of four conditions:
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
.
Figure 5. Management Interface Read Frame Structure
MDC
MDIO
(Read)
High Z
D1
D0
A4
A3
A0
R4
R3
R0
D15
D14
D14
D15
D1
Z
0
32 "1"s
0
1
1
0
Turn
Around
Data
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Write
Read
Datasheet
19
INTEL [ INTEL ]
