LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Figure 6. Management Interface Write Frame Structure
MDC
MDIO
(Write)
A4
A3
A0
R4
R3
R0
D15
D14
D1
D0
32 "1"s
0
1
0
1
0
1
Turn
Around
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Data
Idle
Write
Figure 7. Interrupt Logic
Event X Enable Reg
AND
Event X Status Reg
OR
Port
Combine
Logic
Interrupt Pin
.
.
AND
.
.
.
Per Event
.
Per port
Force Interrupt
Interrupt Enable
1. Interrupt (Event) Status Register is cleared on read.
2. X = Any Interrupt capability
1.3.1
Hardware Control Interface
The LXT9763 provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface consists of three Configuration (CFG) pins for each port.
The CFG pins double as LED drivers. Refer to “Hardware Configuration Settings” on page 23 for
additional details.
1.3.2
MII Data Interface
The LXT9763 supports six standard MIIs (one per port). The MII consists of a data interface and a
management interface. The MII Data Interface passes data between the LXT9763 and one or more
Media Access Controllers (MACs). Separate parallel buses are provided for transmit and receive.
This interface operates at either 2.5 MHz or 25 MHz. The speed is set automatically, once the
operating conditions of the network link have been determined.
1.4
Operating Requirements
1.4.1
Power Requirements
The LXT9763 requires four power supply inputs, VCCD, VCCR, VCCT, and VCCIO. The digital
and analog circuits require 3.3 V supplies (VCCD, VCCR and VCCT). These inputs may be
supplied from a single source although decoupling is required to each respective ground.
20
Datasheet
INTEL [ INTEL ]
