LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 7. Initialization Sequence
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Control
Mode
Low
MDDIS Voltage
Level?
Hardware Control
Mode
High
MDIO Controlled Operation
(MDIO Writes Enabled)
Disable MDIO Read and
Write Operations
Software
Reset?
Yes
No
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
3.4.3
Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
•
•
•
•
28
The LXT971A network port and clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL CORPORATION ]
