LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.4.5
Hardware Configuration Settings
The LXT971A provides a hardware option to set the initial device configuration. The hardware
option uses the three LED driver pins. This provides three control bits, as listed in
The
LED drivers can operate as either open-drain or open-source circuits as shown in
Figure 8. Hardware Configuration Settings
3.3 V
Configuration Bit = 1
LED/CFG Pin
LED/CFG Pin
Configuration Bit = 0
1. The LED/CFG pins automatically adjust their
polarity upon power-up or reset.
2. Unused LEDs may be implemented with pull-up/
pull-down resistors of 10 K.
Table 9.
Hardware Configuration Settings
Desired Mode
LED/CFGn
Pin Settings
1
Resulting Register Bit Values
Control Register
Auto-
Neg
0.12
Speed
0.13
FD
0.8
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
N/A
Auto-Negotiation Adver-
tisement
AN Advertisement Registers
100FD
4.8
100TX
4.7
10FD
4.6
10T
4.5
Auto-
Neg
Speed
(Mbps)
Duplex
Half
Full
Half
Full
Half
Full
Half
Only
Full or
Half
1
Low
Low
Low
Low
High
High
High
High
2
Low
Low
High
High
Low
Low
High
High
3
Low
High
Low
High
Low
High
Low
High
10
Disabled
100
100
Only
Enabled
10/100
0
0
1
1. Refer to
for LED/CFG pin assignments.
30
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL CORPORATION ]
