LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 5. Management Interface Write Frame Structure
MDC
MDIO
(Write)
Idle
32 "1"s
Preamble
0
ST
1
0
1
Op Code
A4
A3
PHY Address
A0
R4
R3
R0
1
0
Turn
Around
D15
D14
Data
D1
D0
Idle
Register Address
Write
3.2.3.1.3
MII Interrupts
The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in
The
LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1, enables
the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status
change on the LXT971A. Interrupts may be caused by four conditions:
•
•
•
•
3.2.3.2
Auto-negotiation complete
Speed status change
Duplex status change
Link status change
Hardware Control Interface
The LXT971A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.
Refer to the Hardware Configuration Settings section on page 30 for additional details.
Figure 6. Interrupt Logic
Even X Mask Reg
AND
Even X Status Reg
OR
NAND
Interrupt Pin (MDINT)
Force Interrupt
Interrupt Enable
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
25
INTEL [ INTEL CORPORATION ]
