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JS28F128P30T85 参数 Datasheet PDF下载

JS28F128P30T85图片预览
型号: JS28F128P30T85
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔的StrataFlash嵌入式存储器 [Intel StrataFlash Embedded Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 102 页 / 1616 K
品牌: INTEL [ INTEL ]
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1-Gbit P30 Family  
8.0  
Power and Reset Specifications  
8.1  
Power Up and Down  
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If  
VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before  
applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN  
.
Power supply transitions should only occur when RST# is low. This protects the device from  
accidental programming or erasure during power transitions.  
8.2  
Reset Specifications  
Asserting RST# during a system reset is important with automated program/erase devices because  
systems typically expect to read from flash memory when coming out of reset. If a CPU reset  
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the  
flash memory may be providing status information, instead of array data as expected. Connect  
RST# to the same active low reset signal used for CPU initialization.  
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during  
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.  
Num Symbol  
Parameter  
RST# pulse width low  
Min  
Max  
Unit  
Notes  
P1  
P2  
P3  
t
t
t
100  
-
ns  
1,2,3,4  
1,3,4,7  
1,3,4,7  
1,4,5,6  
PLPH  
RST# low to device reset during erase  
RST# low to device reset during program  
-
-
25  
25  
-
PLRH  
µs  
V
Power valid to RST# de-assertion (high)  
60  
VCCPH  
CC  
Notes:  
1.  
2.  
3.  
4.  
5.  
6.  
These specifications are valid for all device versions (packages and speeds).  
The device may reset if t is < t MIN, but this is not guaranteed.  
Not applicable if RST# is tied to Vcc.  
Sampled, but not 100% tested.  
PLPH  
PLPH  
If RST# is tied to the V supply, device will not be ready until t  
after V V  
.
CC  
VCCPH  
CC  
CCMIN  
If RST# is tied to any supply/signal with V  
voltage levels, the RST# input voltage must not exceed  
CCQ  
V
until V V  
.
CC  
CC  
CCMIN  
7.  
Reset completes within t  
if RST# is asserted while no erase or program operation is executing.  
PLPH  
April 2005  
46  
Intel StrataFlash® Embedded Memory (P30)  
Order Number: 306666, Revision: 001  
Datasheet  
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