Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 12.
Expansion Bus Interface
Power
Name
On
Reset2 Type†
Description
Reset1
Input clock signal used to sample all expansion interface
inputs and clock all expansion interface outputs.
EX_CLK
Z
Z
Z
0
I
Address-latch enable used for multiplexed address/data bus
accesses. Used in Intel and Motorola* multiplexed modes of
operation.
EX_ALE
O
Expansion-bus address used as an output for data accesses
over the expansion bus. Also, used as an input during reset to
capture device configuration. These signals have a weak pull-
up resistor attached internally. Based on the desired
EX_ADDR[23:0]
H
H
I/O
configuration, various address signals must be tied low in
order for the device to operate in the desired mode.
Intel-mode write strobe / Motorola-mode data strobe
(EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
EX_WR_N
EX_RD_N
Z
Z
1
1
O
O
Intel-mode read strobe / Motorola-mode read-not-write
(EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N).
External chip selects for expansion bus.
•
Chip selects 0 through 7 can be configured to support Intel
or Motorola bus cycles.
EX_CS_N[7:0]
EX_DATA[15:0]
Z
Z
1
0
O
•
Chip selects 4 through 7 can be configured to support TI
HPI bus cycles.
I/O
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices.
Expansion-bus access is halted when an external device sets
EX_IOWAIT_N to logic 0 and resume from the halted location
once the external device sets EX_IOWAIT_N to logic 1. This
signal affects accesses that use EX_CS_N[7:0] when the chip
select is configured in Intel- or Motorola-mode of operation.
EX_IOWAIT_N
H
H
I
Should be pulled high through a 10-KΩ resistor when not
being utilized in the system.
HPI interface ready signals. Can be configured to be active
high or active low. These signals are used to halt accesses
using Chip Selects 7 through 4 when the chip selects are
configured to operate in HPI mode. There is one RDY signal
per chip select. This signal only affects accesses that use
EX_CS_N[7:4].
EX_RDY[3:0]
H
H
I
Should be pulled low though a 10-KΩ resistor when not being
utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
March 2005
44
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
