Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 14.
USB Interface
Power
On
Name
Reset2 Type†
Description
Reset1
USB_DPOS
USB_DNEG
Z
Z
Z
Z
I/O
I/O
Positive signal of the differential USB receiver/driver.
Negative signal of the differential USB receiver/driver.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Table 15.
Oscillator Interface
Power
Name
On
Reset2 Type†
Description
Reset1
33.33 MHz, sinusoidal crystal input signal. Can be driven by an
oscillator.
OSC_IN
I
33.33 MHz, sinusoidal crystal output signal. Left disconnected
when being driven by an oscillator.
OSC_OUT
O
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Table 16.
GPIO Interface (Sheet 1 of 2)
Power
Name
On
Reset2 Type†
Description
Reset1
General purpose Input/Output pins. May be configured as an input
or an output. As an input, each signal may be configured a
processor interrupt. Default after reset is to be configured as inputs.
GPIO[12:0]
Z
Z
I/O
Should be pulled low using a 10-KΩ resistor when not being utilized
in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
March 2005
46
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
