Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 16.
GPIO Interface (Sheet 2 of 2)
Power
Name
On
Reset2 Type†
Description
Reset1
General purpose input/output pins. May be configured as an input
or an output. Default after reset is to be configured as inputs.
GPIO[13]
Z
Z
Z
Z
I/O
I/O
Should be pulled low using a 10-KΩ resistor when not being utilized
in the system.
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an input,
upon reset.
GPIO[14]
GPIO[15]
Should be pulled low though a 10-KΩ resistor when not being
utilized in the system.
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an output,
upon reset. Can be used to clock the expansion interface, after
reset.
CLKOU
T/VO
Z
I/O
Should be pulled low though a 10-KΩ resistor when not being
utilized in the system.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Table 17.
JTAG Interface
Power
Name
On
Reset2 Type†
Description
Reset1
JTG_TMS
JTG_TDI
JTG_TDO
H
H
Z
VI/PE
VI/PE
VO
I
I
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
O
The JTG_TRST_N signal must be asserted (driven low) during
power-up, otherwise the TAP controller may not be initialized
properly, and the processor may be locked.
JTG_TRST_N
JTG_TCK
H
Z
VI/PE
VI
I
I
When the JTAG interface is not being used, the signal must be
pulled low using a 10-KΩ resistor.
Used as the clock for the IEEE 1149.1 JTAG interface.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
47
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
