Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 18.
System Interface††
Power
On
Name
Reset2 Type†
Description
Reset1
Used for test purposes only.
BYPASS_CLK
Z
VI
I
I
Must be pulled high for normal operation.
Used for test purposes only.
SCANTESTMODE_N
H
VI/PE
Must be pulled high for normal operation.
Used as a reset input to the device after power up
conditions have been met. Power up conditions include
the power supplies reaching a safe stable condition and
the PLL achieving a locked state and the
PWRON_RESET_N coming to an active state prior to
the RESET_IN_N coming to an active state.
RESET_IN_N
0
0
VI
VI
I
I
Signal used at power up to reset all internal logic to a
known state after the PLL has achieved a locked state.
The PWRON_RESET_N input is a 1.3-V tolerant only.
PWRON_RESET_N
Used for test purposes only.
HIGHZ_N
H
Z
VI/PE
VO
I
Must be pulled high for normal operation.
Signal used to inform external reset logic that the
internal PLL has achieved a locked state.
PLL_LOCK
O
Signal used to control PCI drive strength characteristics.
Drive strength is varied on PCI address, data and
control signals.
RCOMP
I
Pin requires a 34-Ω +/- 1% tolerance resistor to ground.
Refer to Figure 13 on page 85.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
††
For a legend of the Type codes, see Table 5 on page 33.
IMPORTANT NOTE: When a system-level reset is asserted to the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system
reset, or a Watchdog-Timer reset — and any interface is in an active transaction (particularly the PCI
bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior
of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a
reset of other attached devices may be required.
Table 19.
Power Interface (Sheet 1 of 2)
Name
VCC
Type†
Description
I
I
1.3-V power supply input pins used for the internal logic.
VCCP
VSS
3.3-V power supply input pins used for the peripheral (I/O) logic.
Ground power supply input pins used for both the 3.3-V and the 1.3-V power supplies.
3.3-V power supply input pins used for the peripheral (I/O) logic of the analog
oscillator circuitry.
VCCOSCP
VSSOSCP
I
I
Require special power filtering circuitry. Refer to Figure 11 on page 84
Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry.
Used in conjunction with the VCCOSCP pins.
Requires special power filtering circuitry. Refer to Figure 11 on page 84
†
For a legend of the Type codes, see Table 5 on page 33.
March 2005
48
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
