Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 13.
UART Interfaces
Power
Name
On
Reset2 Type†
Description
Reset1
UART serial data input to High-Speed UART Pins.
RXDATA0
TXDATA0
Z
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a reset operation. High-Speed Serial UART Pins.
VO
O
UART CLEAR-TO-SEND input to High-Speed UART Pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
CTS0_N
RTS0_N
H
H
VI/PE
I
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1).
High-Speed UART Pins.
UART serial data input.
RXDATA1
TXDATA1
Z
Z
VI
I
Should be pulled low through a 10-KΩ resistor when not being
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a Reset operation. Console UART Pins.
VO
O
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
CTS1_N
RTS1_N
H
H
VI/PE
I
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1).
Console UART Pins.
1.
2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
†
For a legend of the Type codes, see Table 5 on page 33.
Datasheet
March 2005
45
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
