MAX 3000A Programmable Logic Device Family Data Sheet
Table 22. EPM3256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tCNT
Minimum global clock
period
(2)
7.9
10.5
ns
MHz
ns
fCNT
Maximum internal global
clock frequency
(2), (4)
(2)
126.6
95.2
95.2
tACNT
fACNT
Minimum array clock
period
7.9
10.5
Maximum internal array
clock frequency
(2), (4)
126.6
MHz
Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2)
Note (1)
Speed Grade
Symbol
Parameter
Conditions
Unit
–7
–10
Min
Max
Min
Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
0.9
0.9
2.8
0.5
2.2
1.0
0.0
1.2
1.2
1.2
3.7
0.6
2.8
1.3
0.0
1.6
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tSEXP
tPEXP
tLAD
tLAC
tIOE
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad delay,
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
tOD2
Output buffer and pad delay,
slow slew rate = off
C1 = 35 pF
C1 = 35 pF
1.7
6.2
2.1
6.6
ns
ns
V
CCIO = 2.5 V
tOD3
Output buffer and pad delay,
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
tZX1
tZX2
Output buffer enable delay, slow C1 = 35 pF
slew rate = off VCCIO = 3.3 V
4.0
4.5
5.0
5.5
ns
ns
Output buffer enable delay, slow C1 = 35 pF
slew rate = off VCCIO = 2.5 V
Altera Corporation
35
INTEL [ INTEL ]
