MAX 3000A Programmable Logic Device Family Data Sheet
Table 21. EPM3128A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max Min
Max
Min
Max
tSU
Register setup time
Register hold time
Register delay
1.4
0.6
2.1
1.0
2.9
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tRD
0.8
1.2
0.9
1.7
1.0
1.6
2.0
2.0
2.0
4.0
1.6
1.3
2.2
1.3
2.0
2.7
2.7
2.6
5.0
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
0.5
1.2
tEN
0.7
tGLOB
tPRE
tCLR
tPIA
tLPA
1.1
1.4
1.4
(2)
(5)
1.4
Low–power adder
4.0
Table 22. EPM3256A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
–7
–10
Min
Max
Min
Max
tPD1
Input to non–registered
output
C1 = 35 pF (2)
7.5
10
ns
ns
tPD2
I/O input to non–registered C1 = 35 pF (2)
output
7.5
4.8
10
tSU
tH
Global clock setup time
Global clock hold time
(2)
5.2
0.0
1.0
6.9
0.0
1.0
ns
ns
ns
(2)
tCO1
Global clock to output
delay
C1 = 35 pF
6.4
9.7
tCH
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
3.0
3.0
2.7
0.3
1.0
3.0
3.0
3.0
4.0
4.0
3.6
0.5
1.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
tCL
tASU
tAH
(2)
(2)
tACO1
tACH
tACL
tCPPW
Array clock to output delay C1 = 35 pF (2)
Array clock high time
7.3
Array clock low time
Minimum pulse width for
clear and preset
(3)
34
Altera Corporation
INTEL [ INTEL ]
