MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3128A External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max
Min
Max
Min
Max
fACNT
Maximum internal
(2), (4)
192.3
129.9
98.0
MHz
array clock frequency
Table 21. EPM3128A Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
–7
Unit
–5
–10
Min
Max Min
Max
Min Max
tIN
tIO
Input pad and buffer delay
0.7
0.7
1.0
1.0
1.4
1.4
ns
ns
I/O input pad and buffer
delay
tSEXP
tPEXP
tLAD
tLAC
tIOE
Shared expander delay
Parallel expander delay
Logic array delay
2.0
0.4
1.6
0.7
0.0
0.8
2.9
0.7
2.4
1.0
0.0
1.2
3.8
0.9
3.1
1.3
0.0
1.6
ns
ns
ns
ns
ns
ns
Logic control array delay
Internal output enable delay
tOD1
Output buffer and pad
delay, slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
Output buffer and pad
delay, slow slew rate = off
VCCIO = 2.5 V
1.3
5.8
4.0
4.5
9.0
4.0
1.7
6.2
4.0
4.5
9.0
4.0
2.1
6.6
ns
ns
ns
ns
ns
ns
Output buffer and pad
delay, slow slew rate = on
V
CCIO = 2.5 V or 3.3 V
Output buffer enable delay, C1 = 35 pF
slow slew rate = off
5.0
V
CCIO = 3.3 V
Output buffer enable delay, C1 = 35 pF
slow slew rate = off
VCCIO = 2.5 V
5.5
Output buffer enable delay, C1 = 35 pF
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
10.0
5.0
Output buffer disable delay C1 = 5 pF
Altera Corporation
33
INTEL [ INTEL ]
