欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM3064ATC100-7N 参数 Datasheet PDF下载

EPM3064ATC100-7N图片预览
型号: EPM3064ATC100-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 711 K
品牌: INTEL [ INTEL ]
 浏览型号EPM3064ATC100-7N的Datasheet PDF文件第34页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第35页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第36页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第37页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第39页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第40页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第41页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第42页  
MAX 3000A Programmable Logic Device Family Data Sheet  
Table 25. EPM3512A Internal Timing Parameters (Part 2 of 2)  
Note (1)  
Speed Grade  
Symbol  
Parameter  
Conditions  
Unit  
-7  
-10  
Min  
Max  
Min  
Max  
tOD3  
Output buffer and pad delay,  
slow slew rate = on  
VCCIO = 2.5 V or 3.3 V  
C1 = 35 pF  
C1 = 35 pF  
C1 = 35 pF  
C1 = 35 pF  
C1 = 5 pF  
6.0  
6.5  
ns  
ns  
ns  
ns  
tZX1  
tZX2  
tZX3  
Output buffer enable delay,  
slow slew rate = off  
4.0  
4.5  
9.0  
4.0  
5.0  
5.5  
V
CCIO = 3.3 V  
Output buffer enable delay,  
slow slew rate = off  
V
CCIO = 2.5 V  
Output buffer enable delay,  
slow slew rate = on  
VCCIO = 3.3 V  
10.0  
5.0  
tXZ  
Output buffer disable delay  
Register setup time  
Register hold time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSU  
2.1  
0.6  
1.6  
1.4  
3.0  
0.8  
1.6  
1.4  
tH  
tFSU  
tFH  
Register setup time of fast input  
Register hold time of fast input  
Register delay  
tRD  
1.3  
0.6  
1.8  
1.0  
1.7  
1.0  
1.0  
3.0  
4.5  
1.7  
0.8  
2.3  
1.3  
2.2  
1.4  
1.4  
4.0  
5.0  
tCOMB  
tIC  
Combinatorial delay  
Array clock delay  
tEN  
Register enable time  
Global control delay  
Register preset time  
Register clear time  
PIA delay  
tGLOB  
tPRE  
tCLR  
tPIA  
tLPA  
(2)  
(5)  
Low-power adder  
Notes to tables:  
(1) These values are specified under the recommended operating conditions, as shown in Table 13 on page 23. See  
Figure 11 on page 27 for more information on switching waveforms.  
(2) These values are specified for a PIA fan–out of one LAB (16 macrocells). For each additional LAB fan–out in these  
devices, add an additional 0.1 ns to the PIA timing value.  
(3) This minimum pulse width for preset and clear applies for both global clear and array controls. The t  
parameter  
LPA  
must be added to this minimum width if the clear or reset signal incorporates the t  
parameter into the signal  
LAD  
path.  
(4) These parameters are measured with a 16–bit loadable, enabled, up/down counter programmed into each LAB.  
(5) The t  
parameter must be added to the t  
, t  
, t , t , t  
, t  
, and t parameters for macrocells  
LPA  
LAD LAC IC EN SEXP ACL  
CPPW  
running in low–power mode.  
38  
Altera Corporation  
 复制成功!