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EPM3064ATC100-7N 参数 Datasheet PDF下载

EPM3064ATC100-7N图片预览
型号: EPM3064ATC100-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 711 K
品牌: INTEL [ INTEL ]
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MAX 3000A Programmable Logic Device Family Data Sheet  
Table 19. EPM3064A Internal Timing Parameters (Part 1 of 2)  
Note (1)  
Symbol  
Parameter  
Conditions  
Speed Grade  
–7  
Unit  
–4  
–10  
Min  
Max Min  
Max  
Min Max  
tIN  
tIO  
Input pad and buffer delay  
0.6  
0.6  
1.1  
1.1  
1.4  
1.4  
ns  
ns  
I/O input pad and buffer  
delay  
tSEXP  
tPEXP  
tLAD  
tLAC  
tIOE  
Shared expander delay  
Parallel expander delay  
Logic array delay  
1.8  
0.4  
1.5  
0.6  
0.0  
0.8  
3.0  
0.7  
2.5  
1.0  
0.0  
1.3  
3.9  
0.9  
3.2  
1.2  
0.0  
1.8  
ns  
ns  
ns  
ns  
ns  
ns  
Logic control array delay  
Internal output enable delay  
tOD1  
Output buffer and pad  
delay, slow slew rate = off  
VCCIO = 3.3 V  
C1 = 35 pF  
C1 = 35 pF  
C1 = 35 pF  
tOD2  
tOD3  
tZX1  
tZX2  
tZX3  
Output buffer and pad  
delay, slow slew rate = off  
VCCIO = 2.5 V  
1.3  
5.8  
4.0  
4.5  
9.0  
1.8  
6.3  
4.0  
4.5  
9.0  
4.0  
2.3  
6.8  
ns  
ns  
ns  
ns  
ns  
Output buffer and pad  
delay, slow slew rate = on  
V
CCIO = 2.5 V or 3.3 V  
Output buffer enable delay, C1 = 35 pF  
slow slew rate = off  
5.0  
V
CCIO = 3.3 V  
Output buffer enable delay, C1 = 35 pF  
slow slew rate = off  
VCCIO = 2.5 V  
5.5  
Output buffer enable delay, C1 = 35 pF  
slow slew rate = on  
VCCIO = 2.5 V or 3.3 V  
10.0  
tXZ  
Output buffer disable delay C1 = 5 pF  
Register setup time  
Register hold time  
4.0  
2.0  
1.0  
0.7  
0.6  
1.2  
0.6  
1.0  
1.3  
5.0  
2.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSU  
1.3  
0.6  
tH  
1.3  
tRD  
Register delay  
1.2  
0.9  
1.9  
1.0  
1.5  
2.1  
1.6  
tCOMB  
tIC  
Combinatorial delay  
Array clock delay  
1.3  
2.5  
tEN  
Register enable time  
Global control delay  
Register preset time  
1.2  
tGLOB  
tPRE  
2.2  
2.9  
Altera Corporation  
31  
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