MAX 3000A Programmable Logic Device Family Data Sheet
Table 23. EPM3256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Speed Grade
Symbol
Parameter
Conditions
Unit
–7
–10
Min
Max
Min
Max
tZX3
Output buffer enable delay, slow C1 = 35 pF
slew rate = on
9.0
10.0
ns
VCCIO = 2.5 V or 3.3 V
tXZ
Output buffer disable delay
Register setup time
Register hold time
Register delay
C1 = 5 pF
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
2.1
0.9
2.9
1.2
tH
tRD
1.2
0.8
1.6
1.0
1.5
2.3
2.3
2.4
4.0
1.6
1.2
2.1
1.3
2.0
3.0
3.0
3.2
5.0
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
tEN
tGLOB
tPRE
tCLR
tPIA
tLPA
(2)
(5)
Low–power adder
Table 24. EPM3512A External Timing Parameters
Note (1)
Symbol Parameter Conditions
Speed Grade
Unit
-7
-10
Min
Max
Min
Max
tPD1
Input to non-registered output C1 = 35 pF (2)
7.5
7.5
10.0
10.0
ns
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF (2)
tSU
tH
Global clock setup time
Global clock hold time
(2)
(2)
5.6
0.0
3.0
7.6
0.0
3.0
ns
ns
ns
tFSU
Global clock setup time of fast
input
tFH
Global clock hold time of fast
input
0.0
0.0
ns
tCO1
tCH
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
C1 = 35 pF
1.0
3.0
3.0
2.5
4.7
1.0
4.0
4.0
3.5
6.3
ns
ns
ns
ns
tCL
tASU
(2)
36
Altera Corporation
INTEL [ INTEL ]
