Timing Model & Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3)
-3 Speed Grade
-4 Speed Grade
-5 Speed Grade
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
tBE
Minimum delay
allowed from the
UFM busy signal
going low to erase
signal going low
20
20
20
ns
tEPMX
tDCO
tOE
Maximum length of
busy pulse during an
erase
500
5
500
5
500
5
ms
ns
ns
Delay from data
register clock to data
register output
Delay from data
register clock to data
register output
180
250
180
250
180
250
tRA
Maximum read
access time
65
65
65
ns
ns
tOSCS
Maximum delay
between the
OSC_ENArising
edge to the
erase/program
signal rising edge
tOSCH
Minimum delay
allowed from the
erase/program
signal going low to
OSC_ENAsignal
going low
250
250
250
ns
5–18
Core Version a.b.c variable
Altera Corporation
July 2006
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
