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EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
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Operating Conditions  
Table 5–9. 1.5-V I/O Specifications  
Symbol  
Parameter  
Conditions  
Minimum  
Maximum  
Unit  
VOL  
Low-level output  
voltage  
0.25 × VCCIO  
V
IOL = 2 mA (1)  
Notes to Tables 5–5 through 5–9:  
(1) This specification is supported across all the programmable drive strength settings available for this I/O standard,  
as shown in the MAX II Architecture chapter (I/O Structure section) of the MAX II Device Handbook.  
(2) This maximum VIH reflects the JEDEC specification. The MAX II input buffer can tolerate a VIH maximum of 4.0 as  
specified by the VI parameter in Table 5–2.  
Table 5–10. 3.3-V PCI Specifications  
Symbol  
Parameter  
Conditions  
Minimum  
Typical  
Maximum  
Unit  
VCCIO  
I/O supply  
voltage  
3.0  
3.3  
3.6  
V
VIH  
VIL  
High-level  
input voltage  
0.5 × VCCIO  
–0.5  
VCCIO + 0.5  
0.3 × VCCIO  
V
V
V
V
Low-level  
input voltage  
VOH  
VOL  
High-level  
output voltage  
IOH = –500 μA  
0.9 × VCCIO  
Low-level  
IOL = 1.5 mA  
0.1 × VCCIO  
output voltage  
Bus Hold Specifications  
Table 5–11 shows the MAX II device family bus hold specifications.  
Table 5–11. Bus Hold Specifications (Part 1 of 2)  
VCCIO Level  
1.8 V 2.5 V  
Min Max Min Max Min Max Min Max  
Parameter  
Conditions  
Unit  
1.5 V  
3.3 V  
Low sustaining  
current  
VIN > VIL (maximum)  
VIN < VIH (minimum)  
20  
30  
50  
70  
μA  
μA  
High sustaining  
current  
–20  
–30  
-50  
–70  
5–8  
Core Version a.b.c variable  
Altera Corporation  
July 2006  
MAX II Device Handbook, Volume 1  
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