EP4CE22E22I7N 参数 Datasheet PDF下载

型号：	EP4CE22E22I7N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 1395 CLBs, 472.5MHz, 22320-Cell, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, EQFP-144]
分类和应用：	时钟LTEPC栅可编程逻辑
文件页数/大小：	44 页 / 663 K
品牌：	INTEL [ INTEL ]

1–24

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 2 of 2)

Performance

Device

Unit

(1)

C8L

362

C9L

265

I8L

—

EP4CE55

500

—

437.5

402

437.5

362

MHz

EP4CE75

362

—

265

—

362

—

EP4CE115

EP4CGX15

EP4CGX22

EP4CGX30

EP4CGX50

EP4CGX75

EP4CGX110

EP4CGX150

Note to Table 1–24:

500

—

(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades.

PLL Specifications

Table 1–25 lists the PLL specifications for Cyclone IV devices when operating in the

commercial junction temperature range (0°C to 85°C), the industrial junction

temperature range (–40°C to 100°C), the extended industrial junction temperature

range (–40°C to 125°C), and the automotive junction temperature range (–40°C to

125°C). For more information about the PLL block, refer to “Glossary” on page 1–37.

Table 1–25. PLL Specifications for Cyclone IV Devices ^{(1), (2)}(Part 1 of 2)

Symbol

Parameter

Input clock frequency (–6, –7, –8 speed grades)

Input clock frequency (–8L speed grade)

Input clock frequency (–9L speed grade)

PFD input frequency

Min

Typ

—

Max

472.5

362

Unit

MHz

(3)

f_IN

265

f_INPFD

325

(4)

f_VCO

PLL internal VCO operating range

Input clock duty cycle

600

1300

f_INDUTY

Input clock cycle-to-cycle jitter

—

0.15

750

(5)

F_REF 100 MHz

t_{INJITTER_CCJ}

F_REF< 100 MHz

f_{OUT_EXT}(external clock

PLL output frequency

472.5

MHz

(3)

output)

PLL output frequency (–6 speed grade)

—

472.5

450

402.5

362

265

MHz

PLL output frequency (–7 speed grade)

f_OUT(to global clock)

PLL output frequency (–8 speed grade)

PLL output frequency (–8L speed grade)

PLL output frequency (–9L speed grade)

Duty cycle for external clock output (when set to 50%)

Time required to lock from end of device configuration

t_OUTDUTY

t_LOCK

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

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EP4CE22E22I7N 参数 Datasheet PDF下载

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