EP4CE22E22I7N 参数 Datasheet PDF下载

型号：	EP4CE22E22I7N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 1395 CLBs, 472.5MHz, 22320-Cell, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, EQFP-144]
分类和应用：	时钟LTEPC栅可编程逻辑
文件页数/大小：	44 页 / 663 K
品牌：	INTEL [ INTEL ]

1–28

Chapter 1: Cyclone IV Device Datasheet

Switching Characteristics

For more information about the supported maximum clock rate, device and pin

planning, IP implementation, and device termination, refer to Section III: System

Performance Specifications of the External Memory Interfaces Handbook.

Actual achievable frequency depends on design- and system-specific factors. Perform

HSPICE/IBIS simulations based on your specific design and system setup to

determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 1–31 through Table 1–36 list the high-speed I/O timing for Cyclone IV devices.

For definitions of high-speed timing specifications, refer to “Glossary” on page 1–37.

Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices ^{(1), (2), (4)}(Part 1 of 2)

C7, I7

C8, A7

C8L, I8L

C9L

Symbol

Modes

Unit

Min Typ Max Min Typ Max Min Typ

Max Min Typ Max Min Typ Max

×10

×8

×7

×4

×2

×1

×10

×8

×7

×4

×2

×1

—

180

360

—

155.5

311

—

155.5

311

—

155.5

311

—

132.5 MHz

265 MHz

265 Mbps

f_HSCLK

(input clock

frequency)

100

360 100

360 80

360 70

360 40

360 20

360 10

311 100

311

Device

operation in

Mbps

t_DUTY

Transmitter

channel-to-

channel skew

(TCCS)

—

200

—

200

—

200

—

200

—

200

Output jitter

(peak to peak)

—

500

—

500

—

550

—

600

—

700

—

20 – 80%,

t_RISE

C_LOAD

5 pF

500

20 – 80%,

t_FALL

C_LOAD

5 pF

—

500

—

500

—

500

—

500

—

500

—

Cyclone IV Device Handbook,

Volume 3

March 2016 Altera Corporation

电子百科

产品导航

EP4CE22E22I7N 参数 Datasheet PDF下载

IC37:专业IC行业平台