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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–29  
Glossary  
Table 1–39. Glossary (Part 3 of 5)  
Letter  
Term  
Definitions  
VCCIO  
VOH  
VIH AC  
(
)
VIH(DC)  
VREF  
VIL(DC)  
VIL(AC  
)
Single-ended  
Voltage  
referenced I/O  
Standard  
VOL  
S
VSS  
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal  
values. The AC values indicate the voltage levels at which the receiver must meet its timing  
specifications. The DC values indicate the voltage levels at which the final logic state of the  
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver  
changes to the new logic state. The new logic state is then maintained as long as the input stays  
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the  
presence of input waveform ringing.  
SW (Sampling  
Window)  
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it  
correctly. The setup and hold times determine the ideal strobe position in the sampling window.  
tC  
High-speed receiver/transmitter input and output clock period.  
TCCS (Channel-  
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,  
to-channel-skew) including tCO variation and clock skew. The clock is included in the TCCS measurement.  
tcin  
tCO  
Delay from clock pad to I/O input register.  
Delay from clock pad to I/O output.  
tcout  
tDUTY  
tFALL  
tH  
Delay from clock pad to I/O output register.  
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.  
Signal High-to-low transition time (80–20%).  
Input register hold time.  
T
Timing Unit  
Interval (TUI)  
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data  
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).  
tINJITTER  
Period jitter on PLL clock input.  
tOUTJITTER_DEDCLK  
tOUTJITTER_IO  
tpllcin  
Period jitter on dedicated clock output driven by a PLL.  
Period jitter on general purpose I/O driven by a PLL.  
Delay from PLL inclk pad to I/O input register.  
Delay from PLL inclk pad to I/O output register.  
tpllcout  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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