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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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1–10  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
Schmitt Trigger Input  
Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,  
nCE  
,
CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the  
input signal for improved noise immunity, especially for signal with slow edge rate.  
Table 1–12 lists the hysteresis specifications across supported VCCIO range for Schmitt  
trigger inputs in Cyclone III devices.  
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices  
Symbol  
Parameter  
Conditions  
Minimum  
200  
Typical  
Maximum  
Unit  
mV  
mV  
mV  
mV  
VCCIO = 3.3 V  
V
V
CCIO = 2.5 V  
CCIO = 1.8 V  
200  
Hysteresis for Schmitt trigger  
input  
VSCHMITT  
140  
VCCIO = 1.5 V  
110  
I/O Standard Specifications  
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH  
and VOL), and current drive characteristics (IOH and IOL) for various I/O standards  
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O  
standard specifications for Cyclone III devices.  
(1), (2)  
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications  
VCCIO (V)  
VIL (V)  
VIH (V)  
Max  
VOL (V)  
VOH (V)  
IOL  
IOH  
I/O Standard  
(mA)  
(mA)  
Min  
3.135  
3.135  
2.85  
Typ  
3.3  
3.3  
3.0  
3.0  
Max  
3.465  
3.465  
Min  
Max  
0.8  
0.8  
0.8  
0.8  
Min  
1.7  
1.7  
1.7  
1.7  
Max  
0.45  
0.2  
Min  
2.4  
(3)  
3.3-V LVTTL  
3.6  
4
2
–4  
–2  
(3)  
(3)  
3.3-V LVCMOS  
3.6  
VCCIO – 0.2  
2.4  
(3)  
3.0-V LVTTL  
3.15 –0.3  
3.15 –0.3  
VCCIO + 0.3  
VCCIO + 0.3  
0.45  
0.2  
4
–4  
3.0-V LVCMOS  
2.85  
VCCIO – 0.2  
0.1  
–0.1  
2.5-V LVTTL and  
LVCMOS  
2.375  
1.71  
1.425  
1.14  
2.85  
2.85  
2.5  
1.8  
1.5  
1.2  
3.0  
3.0  
2.625 –0.3  
1.89 –0.3  
1.575 –0.3  
1.26 –0.3  
0.7  
1.7  
3.6  
0.4  
2.0  
1
2
–1  
–2  
(3)  
1.8-V LVTTL and  
LVCMOS  
0.35 * 0.65 *  
VCCIO VCCIO  
VCCIO  
0.45  
2.25  
0.45  
0.35 * 0.65 *  
VCCIO VCCIO  
0.25 *  
VCCIO  
0.75 *  
VCCIO  
1.5-V LVCMOS  
1.2-V LVCMOS  
3.0-V PCI  
VCCIO + 0.3  
VCCIO + 0.3  
2
–2  
0.35 * 0.65 *  
VCCIO  
0.25 *  
VCCIO  
0.75 *  
VCCIO  
2
–2  
VCCIO  
0.3 *  
VCCIO  
0.5 *  
VCCIO  
3.15  
3.15  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
VCCIO + 0.3 0.1 * VCCIO 0.9 * VCCIO  
1.5  
1.5  
–0.5  
–0.5  
0.35*  
VCCIO  
0.5 *  
VCCIO  
3.0-V PCI-X  
Notes to Table 1–13:  
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”  
in “Glossary” on page 1–27.  
(2) AC load CL = 10 pF.  
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III  
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
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