E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A . (Table 7)
IN
4. Refer to command definition table for valid D . (Table 7)
IN
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configuration (Figure 14), 3.3 V Standard Test component values.
10. See Test Configuration (Figure 14), 5 V High-Speed Test component values.
11. See Test Configuration (Figure 14), 5 V Standard Test component values.
1
2
3
4
5
6
V
IH
ADDRESSES (A)
A
A
IN
IN
V
IL
tAVAV
tAVWH
tWHAX
V
IH
CE# (E)
VIL
tELWL
tWHEH
V
IH
OE# (G)
VIL
tWHWL
tWHQV1,2,3,4
V
IH
WE# (W)
V
IL
tWLWH
tDVWH
tWHDX
V
IH
High Z
Valid
SRD
DATA (D/Q)
D
D
IN
D
IN
IN
V
IL
tPHHWH
tPHWL
tQVPH
6.5V VHH
V
IH
RP# (P)
VIL
V
IH
WP#
VIL
tQVVL
tVPWH
VPPH
2
VPPH
VPPLK
VIL
1
V
(V)
PP
NOTES:
1. V Power-Up and Standby.
CC
2. Write program or Erase Set-Up Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
0530_17
Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)
39
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
