2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Device and
Data
Valid
Standby
Address Selection
V
IH
ADDRESSES (A)
Address Stable
VIL
tAVAV
V
IH
CE# (E)
V
IL
tEHQZ
V
IH
OE# (G)
V
IL
tGHQZ
V
WE# (W) IH
tGLQV
tGLQX
tOH
VIL
tELQV
VOH
DATA (D/Q)
VOL
tELQX
High Z
High Z
Valid Output
tAVQV
V
IH
RP#(P)
VIL
tPHQV
0530_15
Figure 15. AC Waveforms for Read Operations
Device
Address Selection
Data
Valid
Standby
VIH
ADDRESSES (A)
VIL
Address Stable
tAVAV
VIH
CE# (E)
VIL
tEHQZ
tAVFL
VIH
OE# (G)
tELFL
VIL
tGHQZ
VIH
BYTE# (F)
VIL
tGLQV
tELQV
tGLQX
tOH
VOH
tELQX
High Z
High Z
High Z
High Z
High Z
DATA (D/Q)
(DQ0-DQ7)
VOL
Data Output
on DQ0-DQ7
Data Output
on DQ0-DQ7
tAVQV
VOH
DATA (D/Q)
(DQ8-DQ14)
VOL
Data Output
on DQ8-DQ14
t FLQZ
tAVQV
VOH
(DQ15/A-1)
VOL
High Z
Data Output
on DQ15
Address Input
0530_16
Figure 16. BYTE# Timing Diagram for Read Operations
36
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
