2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
NOTES:
See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 11.
12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
1
2
3
4
5
6
VIH
ADDRESSES (A)
VIL
AIN
AIN
tAVAV
tAVEH
tEHAX
VIH
WE# (W)
VIL
tWLEL
tEHWH
VIH
OE# (G)
VIL
VIH
t EHEL
t EHQV1,2,3,4
CE# (E)
VIL
t ELEH
t DVEH
t EHDX
VIH
DATA (D/Q)
VIL
High Z
t PHEL
Valid
SRD
D
D
D
IN
IN
IN
tPHHEH
tQVPH
VHH
6.5V
VIH
RP# (P)
VIL
VIH
WP#
VIL
t VPEH
tQVVL
VPPH2
VPPH
VPPLK
VIL
1
VPP(V)
NOTES:
1. V Power-Up and Standby.
CC
2. Write program or Erase Set-Up Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
0530_18
Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)
42
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
