E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
4.5
AC Characteristics—Commercial (Continued)
Prod
VCC 3.3 ± 0.3V(5) 5V ± 10%(7) 3.3 ± 0.3V(5) 5V ± 10%(7) Unit
Load 50 pF 100 pF 50 pF 100 pF
Notes Min Max Min Max Min Max Min Max
BV-80
BV-120
Sym
Parameter
tAVAV Read Cycle Time
150
80
180
120
ns
ns
ns
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tPHQV RP# to Output Delay
tGLQV OE# to Output Delay
tELQX CE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGLQX OE# to Output in Low Z
tGHQZ OE# to Output in High Z
150
150
0.8
90
80
80
180
180
0.8
90
120
120
2
0.45
40
0.45 µs
2
3
3
3
3
3
40
25
20
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
0
0
0
0
45
45
20
20
45
45
tOH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
tELFL
tELFH
CE# Low to BYTE# High or
Low
3
3
0
0
0
0
ns
ns
tAVFL Address to BYTE# High or
Low
5
5
5
5
tFLQV
tFHQV
BYTE# to Output Delay
3,4
3
150
60
80
30
180
60
120
30
ns
ns
tFLQZ BYTE# Low to Output in
High Z
tPLPH Reset Pulse Width Low
8
150
60
150
60
ns
ns
tPLQZ RP# Low to Output High-Z
150
60
150
60
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE
.
3. Sampled, but not 100% tested.
4.
tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A–1 becomes valid.
5. See Test Configuration (Figure 14), 3.3 V Standard Test component values.
6. See Test Configuration (Figure 14), 5 V High-Speed Test component values.
7. See Test Configuration (Figure 14), 5 V Standard Test component values.
8. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
35
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
