E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
(1, 12)
4.7
AC Characteristics—CE#-Controlled Write Operations
(Continued)
—Commercial
Prod
VCC 3.3 ± 0.3V(9) 5V±10%(11) 3.3 ± 0.3V(9) 5V±10%(11) Unit
Load 50 pF 100 pF 50 pF 100 pF
Notes Min Max Min Max Min Max Min Max
BV-80
BV-120
Sym
Parameter
150
0.8
80
180
0.8
120
ns
tAVAV
tPHEL
Write Cycle Time
0.45
0.45
µs
RP# High Recovery to
CE# Going Low
0
0
0
0
ns
ns
tWLEL
WE# Setup to CE# Going
Low
6,8
200
100
200
100
tPHHEH Boot Block Lock Setup to
CE# Going High
VPP Setup to CE# Going
tVPEH
5,8
3
200
120
100
50
200
150
100
50
ns
ns
High
tAVEH
Address Setup to CE#
Going High
4
120
50
150
50
ns
tDVEH
Data Setup to CE# Going
High
120
0
50
0
150
0
50
0
ns
ns
tELEH
tEHDX
CE# Pulse Width
4
3
Data Hold Time from CE#
High
0
0
0
0
0
0
0
0
ns
ns
tEHAX
Address Hold Time from
CE# High
tEHWH
WE # Hold Time from
CE# High
30
6
30
6
30
6
30
6
ns
tEHEL
CE# Pulse Width High
2,5
µs
tEHQV1
Duration of Word/Byte
Programming Operation
Erase Duration (Boot)
Erase Duration (Param)
Erase Duration(Main)
VPP Hold from Valid SRD
2,5,6
2,5
0.3
0.3
0.6
0
0.3
0.3
0.6
0
0.3
0.3
0.6
0
0.3
0.3
0.6
0
s
s
tEHQV2
tEHQV3
tEHQV4
tQVVL
2,5
s
5,8
ns
ns
RP# VHH Hold from
Valid SRD
6,8
0
0
0
0
tQVPH
7,8
200
100
200
100
ns
tPHBR
Boot-Block Lock Delay
41
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
